The paper “Foundation Model for Analog Layout Generation with Self-Supervised Learning,” by POSTECH Electrical Engineering integrated students Sunkyu Jeong and Wonjun Choi, doctoral student Junung Choi, alumnus Anik Biswas, now at Samsung Electronics, and adviser Professor Byungsub Kim, has been published in IEEE Transactions on Circuits and Systems I (TCAS-I), a leading semiconductor design journal. The team addressed key challenges in foundation models for automatic analog layout generation.

Foundation models, popularized by ChatGPT, are core AI technologies widely used to generate text and images. Pretrained on large datasets and adapted to diverse tasks through fine-tuning, they can improve systematically as more data are added, making them important industrial platforms. Researchers have attempted to apply foundation models to difficult semiconductor design problems but had struggled to find a way forward.

Analog layout is among the hardest semiconductor design stages to automate. Experts still spend long periods drawing numerous geometric patterns individually to meet circuit schematics and design rules, resulting in lengthy development and high costs.

The researchers addressed two core challenges: high-quality design data are scarce because semiconductor designs are company secrets, and manual labeling requires substantial labor; and analog layout patterns are so varied that learning to generate them is difficult.

The team proposed the first self-supervised method for analog layout generation by dividing designs into small parts and reassembling them. From six designs, they produced approximately 320,000 training samples without manual labeling. Through pretraining and fine-tuning, the model successfully performed five different tasks.

These results demonstrate generality and adaptability, key properties of foundation models. The team plans to greatly expand the data to complete a foundation model for analog layout generation.

December 2025.