On February 7, Hwa-sook Cho, an integrated master's/Ph.D. student in POSTECH's Department of Electrical Engineering advised by Professor Jae-yoon Sim, received the Silver Award in Circuit Design at Samsung Electronics' 23rd Humantech Paper Awards for “A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range.”

The paper proposed a phase-locked direct digital synthesizer (PLDDS) architecture for PLL clock generation without a TDC or DCO, allowing the entire circuit to be implemented in Verilog.

This enables reuse across semiconductor processes, achieves the smallest area among published designs, and significantly reduces design costs, with potential for diverse industrial applications.

Of 1,830 submitted papers, 116 received awards.