Seok-ha Hwang, a master's student in POSTECH's Department of Electrical Engineering advised by Professor Young-joo Lee, received a Best Design Award at the 2018 IDEC Congress Chip Design Contest for “Energy efficient symmetric block-wise concatenated BCH decoder for healthy mobile systems.”

He proposed a new error-correcting code structure to maximize NAND-flash storage reliability and implemented a world-class ultrafast, ultralow-power decoder to support it efficiently.

Established in 1995 with support from the Ministry of Trade, Industry and Energy, IDEC supports approximately 300 system semiconductor chip designs annually and holds a yearly contest to identify the best designs.

More than 120 designs were entered this year, and Hwang's design received the top award in the digital category.