Samsung Humantech Paper Award

Affiliation: Department of Electrical Engineering, Analog IC & Systems Laboratory.

Names: Seongyu Lee and Youngsang Kim.

Advisors: Professor Hong-June Park (co-advisor) and Professor Jae-Yoon Sim (primary advisor).

Award: Silver Prize, 15th Samsung Humantech Paper Awards.

Paper: “650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate”—design of a referenceless clock and data recovery circuit that automatically tracks data rates from 650 Mb/s to 8 Gb/s.

Clock and data recovery (CDR) is the most important core block determining the overall performance of a serial communication receiver. In particular, a referenceless CDR circuit that automatically tracks data rates is essential for supporting diverse channel environments and maximizing flexibility, but conventional structures are highly complex and difficult to design.

This study proposed a new dual-loop architecture incorporating a DLL-based frequency-tracking loop, dramatically reducing conventional complexity. Designed and fabricated in a 65 nm CMOS process, the resulting CDR achieved the best performance among reported CDRs in chip size, operating range, and power consumption.

CDR: Clock and Data Recovery.

DLL: Delay-Locked Loop.