Kyung-jun Min and Seong-hyun Park, integrated master's/Ph.D. students, and Hyun-woo Park, a master's student in POSTECH's Department of Electrical Engineering advised by Professor Seok-hyeong Kang, received a 2024 ISOCC Best Poster Award at the 21st International SoC Conference (ISOCC 2024), held August 19–22, 2024, in Sapporo, Japan.

Their research, VeriLogos, uses large language models (LLMs) to generate Verilog RTL code that is syntactically and functionally correct and optimized for post-synthesis power, performance, and area (PPA).

VeriLogos was recognized for reducing errors in manual coding, accelerating design, and lowering the barrier to entry for Verilog HDL programming.