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Professor Profile
Jae-Yoon Sim
Chair Professor심재윤
POSTECH Integrated Circuits and Systems Lab. · LG-201
Background
Education
1995~1999
포항공과대학교 (졸업-전자전기)
1993~1995
포항공과대학교 (졸업-전자전기)
1988~1993
포항공과대학교 (졸업-전자전기)
Experience
Career
2003~2005
Univ.of Southern Cal
1999~2003
삼성전자
Focus
Research Areas
Publications
Journals
국제전문학술지
Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 50, 1263-1274 (2015)
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 62, 1335-1344 (2015)
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer, IEEE Transactions on Biomedical Circuits and Systems, , 9, 138-151 (2015)
EMI Issues in Pseudo-Differential Signaling for SDRAM Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 455-462 (2015)
An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 404-416 (2015)
An In-Band Noise Filtering 32-tap FIR-Embedded Delta Sigma Digital Fractional-N PLL, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 342-348 (2015)
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 326-333 (2015)
Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 184-193 (2015)
An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 155-167 (2015)
Analytical Formulas for Tradeoff Among Channel Loss, Length, and Frequency of RC- and LC-Dominant Single-Ended Interconnects for Fast Equalized Link Tradeoff Estimation, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, , 5, 1497-1506 (2015)
An LCD-VCOM-Noise Resilient Mutual-Capacitive Touch-Sensor IC Chip With a Low-Voltage Driving Signal, IEEE SENSORS JOURNAL, , 15, 4595-4602 (2015)
Characterization and Effects of Ar/Air Microwave Plasma on Wound Healing, PLASMA PROCESSES AND POLYMERS, , 12, 1423-1434 (2015)
A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 579-587 (2014)
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 987-991 (2014)
A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 840-844 (2014)
Ozone-Free Portable Microwave Atmospheric Air Plasma Jet, IEEE TRANSACTIONS ON PLASMA SCIENCE, , 42, 2788-2789 (2014)
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 2618-2630 (2014)
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, , 23, 2093-2102 (2014)
An Approximate Closed-Form Channel Model for Diverse Interconnect Applications, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 61, 3034-3043 (2014)
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 481-485 (2014)
Current-Mode Transceiver for Silicon Interposer Channel, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49
2044-2053 (2014)
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 1682-1693 (2014)
Comparative study between atmospheric microwave and low-frequency plasmas: Production efficiency of reactive species and their effectiveness, JAPANESE JOURNAL OF APPLIED PHYSICS, , 53, – (2014)
Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 463-470 (2014)
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, , 8, 799-809 (2014)
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-mu m CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 48, 516-526 (2013)
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 60, 91-95 (2013)
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 60, 142-146 (2013)
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 48, 2118-2127 (2013)
A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 13, 482-491 (2013)
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 60, 2845-2856 (2013)
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 48, 2795-2804 (2013)
Distinctive plume formation in atmospheric Ar and He plasmas in microwave frequency band and suitability for biomedical applications, PHYSICS OF PLASMAS, , 20, 1-13 (2013)
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 47
2068-2079 (2012)
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping Delta Sigma TDC, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 47, 875-883 (2012)
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 47, 736-743 (2012)
A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 59, 721-725 (2012)
Atmospheric-pressure plasma sources for biomedical applications, PLASMA SOURCES SCIENCE & TECHNOLOGY, , 21, – (2012)
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 46, 435-444 (2011)
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-mu m CMOS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 58, 70-74 (2011)
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 46, 651-659 (2011)
5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 58, 269-273 (2011)
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 46
2053-2063 (2011)
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 58, 687-691 (2011)
A Global Model for the Identification of the Dominant Reactions for Atomic Oxygen in He/O-2 Atmospheric-Pressure Plasmas, PLASMA PROCESSES AND POLYMERS, , 7, 281-287 (2010)
A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 57, 379-383 (2010)
A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter, IEICE TRANSACTIONS ON ELECTRONICS, , E93C, 1333-1337 (2010)
Inactivation of S. mutans Using an Atmospheric Plasma Driven by a Palm-Size-Integrated Microwave Power Module, IEEE TRANSACTIONS ON PLASMA SCIENCE, , 38
1956-1962 (2010)
Introduction to the Special Issue on the 2010 IEEE International Solid-State Circuits Conference, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 45, 2505-2509 (2010)
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 mu m CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 45, 2874-2881 (2010)
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation, IEICE TRANSACTIONS ON ELECTRONICS, , E93C, 1662-1669 (2010)
A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel, IEEE Custom Integrated Circuits Conference, , , – (2010)
A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines, IEEE Custom Integrated Circuits Conference, , , – (2010)
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration, IEICE TRANSACTIONS ON ELECTRONICS, , E93C, 132-135 (2010)
Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces, IEEE TRANSACTIONS ON ADVANCED PACKAGING, , 33, 552-558 (2010)
A Gate-Leakage Insensitive 0.7-V 233-nW ECG Amplifier using Non-Feedback PMOS Pseudo-Resistors in 0.13-mu m N-well CMOS, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 10, 309-315 (2010)
A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 10, 232-239 (2010)
Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, , 19, 15-17 (2009)
A DISTORTION-FREE GENERAL PURPOSE LVDS DRIVER, IEICE TRANSACTIONS ON ELECTRONICS, , E92-C, 278-280 (2009)
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 56, 1645-1656 (2009)
An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 56
2055-2063 (2009)
A Low-Voltage High-Speed CMOS Inverter-Based Digital Differential Transmitter with Impedance Matching Control and Mismatch Calibration, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 9, 14-21 (2009)
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TXData Timing Control, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 44, 2891-2900 (2009)
Deadzone-minimized systematic offset-free phase detectors, IEICE TRANSACTIONS ON ELECTRONICS, , E91-C, 1525-1528 (2008)
A SINGLE-DATA-BIT BLIND OVERSAMPLING DATA-RECOVERY CIRCUIT WITH AN ADD-DROP FIFO FOR USB2.0 HIGH-SPEED INTERFACE, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 55, 156-160 (2008)
A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines, IEEE TRANSACTIONS ON ADVANCED PACKAGING, , 31, 809-817 (2008)
FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links, ELECTRONICS LETTERS, , 44, 272-273 (2008)
Segmented group-inversion coding for parallel links, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 54, 328-332 (2007)
DC-balanced block inversion coding for high-speed links, IEICE TRANSACTIONS ON ELECTRONICS, , E89C
1948-1949 (2006)
Multilevel differential encoding with precentering for high-speed parallel link transceiver, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 40, 1688-1694 (2005)
CHARGE-TRANSFERRED PRESENSING, NEGATIVELY PRECHARGED WORD-LINE, AND TEMPERATURE-INSENSITIVE POWER-UP SCHEMES FOR LOW-VOLTAGE DRAMS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 39, 694-703 (2004)
Offset-compensated direct sensing and charge-recycled precharge schemes for sub-1.0 V high-speed DRAM’s, IEICE TRANSACTIONS ON ELECTRONICS, , E87C, 801-808 (2004)
A PEAK-CURRENT-REDUCED FULL-SWING CMOS OUTPUT DRIVER, IEICE TRANSACTIONS ON ELECTRONICS, , E87C, 1037-1039 (2004)
A. 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 38, 631-640 (2003)
A CMOS TRANSCEIVER FOR DRAM BUS SYSTEM WITH A DEMULTIPLEXED EQUALIZATION SCHEME, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 37, 245-250 (2002)
FULL-SWING CMOS OUTPUT DRIVER USING ON-CHIP CAPACITORS, WITH FAST RISE TIME AND SMALL OVERSHOOT”, ELECTRONICS LETTERS, , 37, 484-485 (2001)
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 34, 529-535 (1999)
Analysis and prevention of DRAM latch-up during power-on, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 32, 79-85 (1997)
Adaptive biasing folded cascode CMOS OP amp with continuous-time push-pull CMFB scheme, IEICE TRANSACTIONS ON ELECTRONICS, , E80C, 1203-1210 (1997)
일반학술지
A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition, Journal of Electrical and Computer Engineering, , 2011, 1-7 (2011)
A 1.2V 7-BIT 1GS/S CMOS FLASH ADC WITH CASCADED VOTING AND OFFSET CALIBRATION, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , , – (2008)
A SSN-REDUCED 5GB/S PARALLEL TRANSMITTER, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , , – (2007)
CIRCUITS DESIGN OF DRAM FOR MOBILE GANERATION, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , , – (2007)
A design guide of 3-stage CMOS operational amplifier with nested Gm-C frequency compensation, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 7, 20-27 (2007)
Conference
Conference Papers
All-synthesizable 5-phase Phase-Locked Loop, ICEIC 2016, 0, 0, – (2016)
All-synthesizable current-mode transmitter driver for serial link interface, ICEIC 2016, 0, 0, – (2016)
A Reduced-Size Look-Up-Table for ADC Sample-Times of a Single-Chip Non-Uniform-Sampling Digital-Beamformer for Ultasound Medical Imaging, ISOCC, 0, 0, – (2015)
Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design, IEEE/ACM INTERNATIONAL COMPUTER-AIDED DESIGN CONFERENCE, 0, 0, – (2015)
An Approximate Condition to Avoid Reverse Leakage Current in ReRAM Crossbar Design, IEEE INTERNATIONAL SOC DESIGN CONFERENCE, 0, 0, – (2015)
A Mutual-Capacitive Touch Sensor ROIC Using a PLL to Reduce LCD Noise by Synchronizing ROIC TX Clock to LCD Clock, IEEE SENSORS CONFERENCE, 0, 0, – (2015)
An ultra-low-power biomedical chip for injectable pressure monitor, IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE, 0, 0, – (2015)
A 35dB-Linear Variable Gain Amplifier Circuit of Digital-Beamformer for Ultrasound Medical Imaging, ITC-CSCC, 0, 0, – (2015)
High-speed USB 2.0 device 용 Link 및 Data Acquisition System, 대한전자공학회 하계학술대회, 0, 0, – (2015)
Energy-Efficient CDCs for Millimeter Sensor Nodes, ADVANCES IN ANALOG CIRCUIT DESIGN (AACD), 0, 0, – (2015)
A 29-nW bandgap reference circuit, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 0, 0, – (2015)
EMI issues in pseudo-differential signaling for SDRAM interface, 제 22회 한국반도체 학술대회, 0, 0, – (2015)
Voltage-Scalable 10-b Pipelined ADC with Current-Mode Amplifier, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 0, 0, – (2014)
A 0.4 V Driving Multi-Touch Capacitive Sensor with the Driving Signal Frequency set to (n+0.5) Times the Inverse of the LCD VCOM Noise Period, DIGEST OF TECHNICAL PAPERS – IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 682-685 (2014)
오픈루프 시간차이 증폭기를 이용한 고해상도 Time-to-Digital Converter, 대한전자공학회 SOC 학술대회, 0, 0, – (2014)
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling, 대한전자공학회 SOC 학술대회, 0, 0, – (2014)
수신 단 TIA 터미네이션 기법의 단일 신호선 듀오바이너리 송수신 단 회로, 대한전자공학회 SOC 학술대회, 0, 0, – (2014)
LCD VCOM Noise 주파수 (n+0.5) 배의 주파수를 인가 신호 주파수로 이용하는 다중 정전용량 터치 센서, 대한전자공학회 SOC 학술대회, 0, 0, – (2014)
CMOS 이미지 센서 인터페이스용 Gb/s SerDes, 대한전자공학회 SOC 학술대회, 0, 0, – (2014)
Single-Stage 40dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Analog Front End, 한국반도체학술대회, 0, 0, – (2014)
An Analog-Digital-Hybrid Single-Chip RX Beamformer with Non-Uniform Sampling for 2D-CMUT Ultrasound Imaging to Achieve Wide Dynamic Range of Delay and Small Chip Area, DIGEST OF TECHNICAL PAPERS – IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 426-427 (2014)
A 160nW 63.9fJ/conversion-step Capacitance-to-Digital Converter for Ultra-Low-Power Wireless Sensor Nodes, DIGEST OF TECHNICAL PAPERS – IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 220-221 (2014)
A Coefficient-Error-Robust FFE TX with 230% Eye-Variation Improvement Without Calibration in 65nm CMOS Technology, DIGEST OF TECHNICAL PAPERS – IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 50-51 (2014)
A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface, DIGEST OF TECHNICAL PAPERS – IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 48-49 (2014)
Full-speed USB 2.0 device 용 Link 및 Application layer 칩, 대한전자공학회 추계학술대회 논문집, 0, 0, 43-46 (2013)
Verilog Synthesis of USB 2.0 Full-speed Device PHY IP, ISOCC, 0, 0, – (2013)
A Power reduction of 37% in a Differential Serial Link Transceiver by Increasing the Termination Resistance, PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 0, 0, 221-224 (2013)
45pW ESD Clamp Circuit for Ultra-Low Power Applications, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 0, 0, – (2013)
65nW CMOS Temperature Sensor for Ultra-Low Power Microsystems, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 0, 0, – (2013)
All-digital USB 2.0 device Full-speed PHY 칩, 대한전자공학회 하계학술대회, 0, 0, – (2013)
High slew-rate 1.2V Class-AB OTA, ITC-CSCC, 0, 0, 222-224 (2013)
A Measurement-Based Time and Frequency Domain Analysis of the LCD VCOM Noise, SID SYMPOSIUM DIGEST OF TECHNICAL PAPERS, 0, 0, 1501-1504 (2013)
RC-dominant 채널의 간단한 전달 함수모델을 이용한 RC-dominant 인터커넥트 채널의 길이와 손실의 Trade-off 분석, 대한전자공학회 SOC 학술대회, 0, 0, – (2013)
A 27% Reduction in Transceiver Power for Single-Ended Point-to-Point DRAM Interface with the Termination Resistance of 4xZ0 at both TX and RX, ISSCC, 0, 0, 308-310 (2013)
A 95fJ/b Current-Mode Transceiver for 10mm On-Chip Interconnect, ISSCC, 0, 0, 262-264 (2013)
A 0.45V 423nW 3.2MHz Multiplying DLL with Leakage-Based Oscillator for Ultra-Low-Power Sensor Platforms, ISSCC, 0, 0, 188-190 (2013)
A Winner-Take-All Neuromorphic IC in 65nm CMOS, 한국반도체학술대회, 0, 0, – (2013)
A Neuromorphic IC with Spike-Timing-Dependent-Plasticity, 한국반도체학술대회, 0, 0, – (2013)
A 416-kS/s 12-bit algorithmic ADC compensating capacitance mismatch of MDAC in digital domain, ICEIC, 0, 0, – (2013)
델타-시그마 기법을 이용한 USB3.0 어플리케이션용 스프레드 스펙트럼 클락 생성기, 대한전자공학회 추계학술대회, 0, 0, – (2012)
저항형 센서를 위한 연관된 중복 샘플 방식의 인터페이스 회로, 한국센서학회 종합학술대회, 0, 0, 78-78 (2012)
A Spread Spectrum Clock Generator Using Phase/Frequency Boosting with a Peak Power Reduction 14.6dB, RMS Jitter 1.45ps and Power 4.8mW/GHz for USB 3.0, ASSCC, 0, 0, – (2012)
A Single-Chip Time-Interleaved 32-Channel Analog Beamformer for Ultrasound Medical Imaging, ASSCC, 0, 0, – (2012)
An On-chip TSV Emulation Using Metal Bar Surrounded by Metal Ring to Develop Interface Circuits, ISOCC, 0, 0, 192-195 (2012)
A Fractional-N Frequency Divider for SSCG Using a Single Dual-Modulus Integer Divider and a Phase Interpolator, ISOCC, 0, 0, 68-71 (2012)
A 0.5V, 11.3-μW, 1-kS/s Resistive Sensor Interface Circuit with Correlated Double Sampling, CICC, 0, 0, – (2012)
A 10-Touch Capacitive-Touch Sensor Circuit with the Time-Domain Input-Node Isolation, SID SYMPOSIUM DIGEST OF TECHNICAL PAPERS, 0, 0, 493-496 (2012)
NCO 용 Pulse Width Modulator 회로, 대한전자공학회 SOC 학술대회, 0, 0, – (2012)
A 5Gb/s Single-Ended Parallel Receiver with Adaptive FEXT Cancellation, ISSCC, 0, 0, 140-141 (2012)
An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface, ISSCC, 0, 0, 136-137 (2012)
공정산포 자체 보정 기능을 갖는 Winner-Take-All Neuromorphic 시스템 회로 설계, 대한전자공학회 추계학술대회, 0, 0, – (2011)
Time-Interleaved Sample Clock Generator for Ultrasound Beamformer Application, ISOCC, 0, 0, 290-293 (2011)
A High-Gain Wide-Input-Range Time Amplifier with an Open-Loop Architecture and a Gain Equal to Current Bias Ratio, ASSCC, 0, 0, 325-328 (2011)
Digital-Domain Calibration of Split-Capacitor DAC with no Extra Calibration DAC for a Differential-Type SAR ADC, ASSCC, 0, 0, 77-80 (2011)
센서 인터페이스 응용을 위한 0.5 V 100 kS/s 13b SAR A/D 변환기, 한국센서학회 종합학술대회 논문집, 0, 0, 134-134 (2011)
Phase-Blender-Based FIR Noise Filtering Techniques for ΔΣ Fractional-N PLL, MWSCAS, 0, 0, – (2011)
USB 2.0 Protocol Layer의 FPGA 구현과 검증, 대한전자공학회 하계종합학술대회, 0, 0, 376-379 (2011)
PCB상에 구현한 Mutual Capacitive 방식의 Multi-Touch pad, 대한전자공학회 하계종합학술대회, 0, 0, 338-341 (2011)
Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits, ITC-CSCC, 0, 0, – (2011)
Reduction in the Peak Frequency Spectrum of Clock-Embedded Data-Signal for TFT-LCD Compared With the Regular-Clock and PRBS-Data Signals, ITC-CSCC, 0, 0, – (2011)
A 0.63ps Resolution, 11b Pipeline TDC in 0.13μm CMOS, SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, 0, 0, 152-153 (2011)
A 2 GHz Fractional-N Digital PLL with lb Noise Shaping ΔΣ TDC, SYMPOSIUM ON VLSI CIRCUITS DIGETS OF TECHNICAL PAPERS, 0, 0, 116-117 (2011)
센서 인터페이스용 14비트 Cyclic ADC의 설계, 대한전자공학회 SOC 학술대회, 0, 0, 58-61 (2011)
A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering, ISSCC, 0, 0, 94-95 (2011)
A 0.7-V 233-nW Analog CMOS Front-End Circuit for Portable Heart-Rate Monitor, 한국반도체학술대회, 0, 0, 127-128 (2011)
Wide Gain Range와 dB-Linear 특성을 가진 저전력 CMOS 가변 이득 증폭기, 대한전자공학회 추계종합학술대회, 0, 0, 14-15 (2010)
A Transmitter with Different Output Timing to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines, ISOCC, 0, 0, 364-367 (2010)
Verilog를 이용한 USB Serial Interface Engine 설계, 대한전자공학회 연합학술대회, 0, 0, – (2010)
A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel, CICC, 0, 0, – (2010)
A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines, CICC, 0, 0, – (2010)
TX Digital Circuit for USB 2.0 PHY High Speed Interface, ICEIC, 0, 0, – (2010)
Digital Circuit of USB 2.0 PHY High Speed RX Interface, ICEIC, 0, 0, – (2010)
High-Speed Links for Memory Interface, ICICDT, 0, 0, 16-19 (2010)
A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization, SID SYMPOSIUM DIGEST OF TECHNICAL PAPERS, 0, 0, 62-65 (2010)
Two-coupled 마이크로스트립 라인의 SPICE RLGC 파라미터 추출, 대한전자공학회 SOC 학술대회, 0, 0, – (2010)
A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18um CMOS, INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 0, 0, – (2010)
시그마-SPICE : 멀티 코어 CPU용 병렬 모드 SPICE, 대한전자공학회 대전충남지부 학술대회, 0, 0, – (2009)
55% Data Rate Increase of SSTL DRAM Interface Channels by Eliminating Crosstalk-Induced Jitter, 대한전자공학회 추계종합학술대회, 0, 0, 21-22 (2009)
An Analytic Decision Method for the Feed-forward Equalizer Tap-Coefficients at Transmitter, ISOCC, 0, 0, 400-403 (2009)
A 5-7 Gbps Peak Detector for Serial-Link, ISOCC, 0, 0, – (2009)
A 1.3uW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18um CMOS, SYMPOSIUM ON VSLI CIRCUITS, 0, 0, – (2009)
시그마-SPICE : SPICE3 기반의 혼성모드 및 병렬 몬테카를로 회로 시뮬레이터, 대한전자공학회 SOC 학술대회, 0, 0, 440-443 (2009)
An 11.4mW 3Gbps 0.18μm CMOS Digital Differential Transmitter with Calibrations of Termination and Pre-Driver Mismatch, 한국반도체학술대회, 0, 0, – (2009)
RFID Reader 용 14b 연속시간 ΔΣ A/D 변환기, 한국반도체학술대회, 0, 0, – (2009)
A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate, ISSCC, 0, 0, – (2009)
A 1V 2.8Gbps 0.18µm CMOS Inverter-Based Digital Cifferential Transmitter with Calibrations of Termination and Misnatch, ISOCC, 0, 0, – (2008)
A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization, ISOCC, 0, 0, – (2008)
A 4Gbps 3-bit parallel Transmitter with the Crosstalk-Induced Jitter Compensation using TX Data Timing Control, ASSCC, 0, 0, – (2008)
A Transister-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL, ASSCC, 0, 0, – (2008)
A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface, ASSCC, 0, 0, – (2008)
A Low-Voltage OP Amp with Digitally Controlled Algorithmic Approximation, CICC, 0, 0, – (2008)
A Time-Domain Analytic Equation of Supply Voltage Droop in CMOS Output Drivers, 한국반도체학술대회, 0, 0, 908-909 (2008)
A 480MHz 5-phase digital DLL using current controlled delay line, 한국반도체학술대회, 0, 0, 743-744 (2008)
A 1.2V 7-bit 1GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration, 한국반도체학술대회, 0, 0, 65-66 (2008)
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration, ISSCC, 0, 0, – (2008)
A 5Gb/s 16-bit Transmitter with Segmented Group-Inversion Encoding, ISOCC, 0, 0, – (2007)
A Serpentine Guard Trace to Reduce the Far-end Crosstalk Induced Jitter of Parallel Microstrip Lines, ISOCC, 0, 0, – (2007)
An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6Gbps DDR interface, IEEE Custom Integrated Circuit Conference, 0, 0, 373-376 (2007)
Serpentine guard trace to reduce far-end crosstalk and even-odd mode velocity mismatch of microstrip lines by more than 40%, Electronic Components and Technology Conference, 0, 0, 329-332 (2007)
A-40-to-800MHz Locking Multi-Phase DLL, ISSCC, 0, 0, – (2007)
A 256Mb SDRAM with effectively precharged negative word-line scheme, 한국 반도체 학술 대회, 0, 0, 271-272 (2003)
Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs, SOVC, 0, 0, – (2003)
Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs, Symposium on VLSI Circuits, 0, 0, 289-292 (2003)
A 1.8V 128Mb Mobile DRAM with Triple Pumped VPP, Hybrid Current Sense Amplifier, 한국 반도체 학술 대회, 0, 0, 25-29 (2003)
A 1.0V 256Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes, ISSCC, 0, 0, – (2003)
A 1.0V 256Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes, International Solid-State Circuit Conference, 0, 0, 310-311 (2003)
A 1.8V 128Mb Mobile DRAM with Triple Pumped VPP, Hybrid Current Sense Amplifier, 한국 반도체 학술 대회, 0, 0, 275-276 (2003)
Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs, Symposium on VLSI Circuits, 0, 0, – (2003)
Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs, SOVC, 0, 0, – (2002)
Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs, Symposium on VLSI Circuits, 0, 0, 294-297 (2002)
A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture, ISSCC, 0, 0, – (2001)
A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture, International Solid-State Circuit Conference, 0, 0, 378-379 (2001)
840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication, SOVC, 0, 0, – (1999)
840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication, Symposium on VLSI Circuits, 0, 0, 23-24 (1999)
Design of a micro-controller imbedded successive approximated 12bit A/D converter, 한국 반도체 학술 대회, 0, 0, 300-301 (1999)
Investigation of requirements for high-speed DRAM interface using Rambus-C as an example, ICVC, 0, 0, – (1997)
1Gb/s current mode bi-directional I/O buffer, Symposium on VLSI Circuits, 0, 0, 121-122 (1997)
1Gb/s current mode bi-directional I/O buffer, SOVC, 0, 0, – (1997)
Investigation of requirements for high-speed DRAM interface using Rambus-C as an example, International Conference of VLSI and CAD, 0, 0, 118-120 (1997)
Design of 1.2V 10bit cyclic A/D converter using a conventional high-threshold digital CMOS technology, 한국 반도체 학술 대회, 0, 0, 411-412 (1996)
A large-slew-rate fully differential folded cascode CMOS OP amp with adaptive bias, International Conference of VLSI and CAD, 0, 0, 59-62 (1995)
A large-slew-rate fully differential folded cascode CMOS OP amp with adaptive bias, ICVC, 0, 0, – (1995)
A global minimum finding SPICE model parameter extraction program using the fast simulated diffusion algorithm with application to BSIM1, BSIM3, level3 and Gummel-Poon models, ICVC, 0, 0, – (1993)
A global minimum finding SPICE model parameter extraction program using the fast simulated diffusion algorithm with application to BSIM1, BSIM3, level3 and Gummel-Poon models, International Conference of VLSI and CAD, 0, 0, 135-138 (1993)
A 40-to-800MHz Locking Multi-Phase DLL, IEEE International Solid-State Circuit Conference, 0, 0, 306-307 (0000)
Serpentine guard trace to reduce far-end crosstalk and even-odd mode velocity mismatch of microstrip lines by more than 40%, Electronic Components and Technology Conference, 0, 0, 329-332 (0000)
An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6Gbps DDR interface, IEEE Custom Integrated Circuit Conference, 0, 0, 373-376 (0000)
A 5 Gb/s 16-bit transmitter with segmented group-inversion encoding, International SoC Design Conference, 0, 0, 223-226 (0000)
A serpentine guard trace to reduce the far-end crosstalk induced jitter of parallel microstrip lines, International SoC Design Conference, 0, 0, 211-214 (0000)
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration, ISSCC2008 accepted for publication, 0, 0, 112-113600 (0000)
Highlights
Research Achievements
저전력 메모리 회로 설계, 포항공과대학교 (2005-2006)
저전력 메모리 회로 설계, 포항공과대학교 (2006-2006)
고속 저전력 DRAM용 입출력 시스템 개발, [삭제]삼성전자(주)기흥공장 (2006-2007)
ON-CHIP THERMOMETER 개발, (주)하이닉스반도체 (2006-2007)
차세대 12배속 BLU-RAY WSC용 고속 DLL 및 LVDS DRIVER 개발, [삭제]삼성전자(주)기흥공장 (2006-2007)
시각 센서 인터페이스 및 고속 INTRA 칩 통신을 위한 저전력 고속 LVDS 송수신기 설, 전자부품연구원 (2006-2007)
고속 HDMI 인터페이스 회로설계, 삼성전자(주) (2007-2008)
인건비풀링과제, 포항공과대학교 (2007-2015)
자체연구개발과제, 포항공과대학교 (2007-2016)
복합 센서용 신호처리 ADC 기술 개발, 전자부품연구원 (2007-2008)
시각 센서 인터페이스 및 고속 INTRA 칩 통신을 위한 저전력 고속 LVDS 송수신기 설계, 전자부품연구원 (2007-2008)
ON-CHIP THERMOMETER 개발, (주)하이닉스반도체 (2007-2008)
멀티미디어 인터페이스 관련 IP 개발, 인하대학교 (2007-2007)
모바일 RFID 리더 SOC 개발, 한화테크윈(주) (2007-2008)
PCIE PHY IP의 PLL/SERDES/TX-AFE/로직회로, 전자부품연구원 (2007-2008)
LOW VOLTAGE DC GENERATOR 개발, (주)하이닉스반도체 (2008-2009)
고속인터페이스 회로 IP 연구, 인하대학교 산학협력단 (2008-2008)
복합 센서용 신호처리 ADC 기술 개발, 전자부품연구원 (2008-2009)
선행 핵심 IP 기술 개발 – 고속 인터페이스 IP, 전자부품연구원 (2008-2009)
고속 저전력 MOBILE 메모리 인터페이스, 삼성전자(주) (2008-2009)
링크 CDR 개발, (주)에이디테크놀로지 (2009-2009)
LOW VOLTAGE DRAM의 SENSING MARGIN 개선 기술 연구, (주)하이닉스반도체 (2009-2010)
융복합 센서 인터페이스 칩 설계, 포항공과대학교 (2010-2011)
고속 저전력 MOBILE 메모리 인터페이스, 삼성전자(주) (2010-2011)
LOW VOLTAGE DRAM의 SENSING MARGIN 개선 기술 연구, (주)하이닉스반도체 (2010-2011)
뉴로모픽 시스템 회로 연구, 삼성전자(주) (2010-2011)
단일칩 마이크로파 플라즈마 생성장치 개발, 재단법인한국연구재단 (2010-2011)
(학생)인건비풀링과제, 포항공대산학협력단 (2010-2020)
센서 인터페이스용 초저전력 아날로그-디지털 변환기 설계 (학, 포항공과대학교 (2010-2010)
연구/관측용 저고도 자동제어 비행선, 포항공과대학교 (2010-2011)
GSM/EDGE PHASE MODULATION ALL-DIGITAL PLL IP 개발, 삼성전자(주) (2011-2012)
아날로그 집적회로 기반 나노스케일 뉴로모픽 시스템 연구, 재단법인한국연구재단 (2011-2012)
단일칩 마이크로파 플라즈마 생성장치 개발, 재단법인한국연구재단 (2011-2012)
3GBPS급 디지털 아날로그 변환기 구조 연구 및 IP 개발, 전자부품연구원 (2011-2012)
FAST LOCK ALL-DIGITAL PLL의 개발, 에스케이하이닉스 주식회사 (2011-2012)
초저전력 범용 센싱 플랫폼 칩 개발, (주)포스코 (2011-2011)
QUAD SKEW 자체 보상용 고속 메모리 IO 기술 개발, 삼성전자(주) (2011-2012)
스마트폰 및 스마트 TV용 SOC를 위한 아날로그 및 인터페이스 IP 개발, 한국산업기술평가관리원 (2011-2012)
UNIVERSAL BOARD 향 ANALOG 회로 개발, 삼성전자(주) (2011-2012)
뉴로모픽 칩 설계 연구, 삼성전자(주) (2011-2012)
의료용 플라즈마 드라이버 칩 설계, 포항공대산학협력단 (2011-2011)
아날로그 집적회로 기반 나노스케일 뉴로모픽 시스템 연구, 재단법인한국연구재단 (2012-2013)
단일칩 마이크로파 플라즈마 생성장치 개발, 재단법인한국연구재단 (2012-2013)
스마트폰 및 스마트 TV용 SOC를 위한 아날로그 및 인터페이스 IP 개발, 한국산업기술평가관리원 (2012-2013)
저전압 기준전압 생성회로 연구, 삼성전자(주) (2012-2013)
FAST LOCK, LOW JITTER ADPLL 설계 기술 개발, 에스케이하이닉스 주식회사 (2012-2014)
CMOS 이미지 센서용 고속 직렬 링크, (주)픽셀플러스 (2013-2014)
스마트폰 및 스마트 TV용 SOC를 위한 아날로그 및 인터페이스 IP 개발, 한국산업기술평가관리원 (2013-2015)
아날로그 집적회로 기반 나노스케일 뉴로모픽 시스템 연구, 재단법인한국연구재단 (2013-2014)
뇌를 모사하며 학습하는 이미지 프로세서 유닛, 재단법인한국연구재단 (2014-2015)
(정인교_무학과)소형로봇 정밀제어를 위한 모터 개발(대학), 포항공과대학교 (2014-2015)
저전력 SSCG ADPLL 설계 기술 개발, 에스케이하이닉스 주식회사 (2014-2015)
소형 플라즈마 구동 IC 개발, 메디플 (2015-2016)
뇌를 모사하며 학습하는 이미지 프로세서 유닛, 재단법인한국연구재단 (2015-2016)
초연결 스마트 모바일 서비스를 위한 5G 이동통신 핵심기술 개발, 한국전자통신연구원 (2015-2016)
NEUROMORPHIC DVS SYSTEM 설계 자문, 삼성전자(주) (2015-2015)
자체연구개발과제[2015년 신설], 포항공과대학교 (2015-2034)
초저전력 센서 인터페이스 IC 개발, (재)포항산업과학연구원 (2015-2016)
[AP_TP과제]초저전력 센서 인터페이스 IC 개발, (재)포항산업과학연구원 (2015-2016)
휴대용 저전력 마이크로파 플라즈마 의료기기를 위한 전력 모듈 개발, 재단법인한국연구재단 (2015-2016)
SENSOR INTERFACE를 위한 저전력 14BIT SAR ADC IP 상용화 개발, 씨자인 (2015-2016)
고속 직렬 트랜시버 회로기술 개발, 삼성전자(주) (2016-2017)
뇌를 모사하며 학습하는 이미지 프로세서 유닛, 재단법인한국연구재단 (2016-2017)
TEMPORAL LEARNING 신경망모사 회로 설계, 한국과학기술연구원 (2016-2016)
뉴로모픽 칩을 위한 뉴런셀 및 시냅스의 저전력 회로 기술 연구, 한국전자통신연구원 (2016-2016)
휴대용 저전력 마이크로파 플라즈마 의료기기를 위한 전력 모듈 개발, 재단법인한국연구재단 (2016-2017)
[AP-TP]가스센서 전용 센서 인터페이스 IC 상용화 기술 개발, (재)포항산업과학연구원 (2016-2017)
Intellectual Property
IP
심재윤,이민섭,정인화,김용주, 완전 디지털 위상 고정 루프, 한국, 10-2016-0178753 (2016)
지영우,심재윤, 저전력 밴드갭 기준전압 및 기준전류 동시 발생 회로, 한국, 10-2016-0170157 (2016)
심재윤,구자현, 주파수 오차 보상 루프를 이용한 직교 위상 이완 발진기, 한국, 10-2016-0170156 (2016)
심재윤,조화숙, 직접 디지털 주파수 합성기를 이용한 위상 고정루프, 한국, 10-2016-0182938 (2016)
심재윤,손현우, 디지털-아날로그 변환기와 아날로그-디지털 변환기를 이용한 비트 직렬 곱셈누적 연산기, 한국, 10-2016-0164380 (2016)
한세광,금도희,심재윤,구자현,이건희, 광치료용 스마트 무선구동 콘택트렌즈, 한국, 10-2016-0129032 (2016)
심재윤,손현우, 전력 소모량 및 동적범위가 개선된 전류 판독 회로, 한국, 10-2016-0115637 (2016)
심재윤,이종미,지영우, 리퀴지 전류를 이용한 저전력 밴드갭 기준전압 발생 회로, USA, 15/150,564 (2016)
심재윤,홍승환, 주입 고정식 디지털 주파수 신시사이저 회로, USA, 14/910,129 (2015)
심재윤,지영우,이종미, 리퀴지 전류를 이용한 저전력 밴드갭 기준전압 발생 회로, 한국, 10-2015-0067942 (2015)
심재윤,조화숙,김준석,류현석, 시냅스 어레이, 펄스 쉐이퍼 회로 및 이들을 포함하는 뉴로모픽 시스템, 한국, 10-2014-0016336 (2015)
심재윤,백동훈,이동명,이재열, 디스플레이 구동 회로, USA, 14/606,282 (2015)
심재윤,김신웅,김용주,정인화, 분수형 완전 디지털 위상 고정 루프, 반도체 장치 및 휴대 정보 기기, 한국, 10-2014-0174654 (2014)
심재윤,백동훈,이동명,이재열, 디스플레이 구동 회로, 한국, 10-2014-0158279 (2014)
심재윤,홍승환, 주입 고정식 디지털 주파수 신시사이저 회로, -, PCT/KR2014/0073 (2014)
심재윤,지영우,조화숙, 하드웨어 기반의 신경망을 이용한 사용자 적응형 언어 보조기기, 한국, 10-2014-0116186 (2014)
심재윤,서윤재,최승남, 저항의 변화를 이용한 클래스 AB 증폭 장치, 한국, 10-2014-0055456 (2014)
심재윤,김준석,류현석, 시냅스 어레이, 펄스 쉐이퍼 회로 및 이들을 포함하는 뉴로모픽 시스템, 한국, 10-2013-0065669 (2014)
심재윤,조화숙, 아날로그 디지털 변환기의 커패시터 부정합 효과를 줄이기 위한 커패시터 분할 및 교환을 통한 디지털 배경 보정기법, USA, 14/185,950 (2014)
심재윤,홍승환,이현배, 완전 디지털 위상 고정 루프 회로, 반도체 장치 및 휴대 정보 기기, 한국, 10-2013-0082118 (2013)
심재윤,홍승환, 주입 고정식 디지털 주파수 신시사이저 회로, 한국, 10-2013-0103808 (2013)
심재윤,서윤재,최승남, 전류차를 이용한 클래스 AB 증폭 장치 및 방법, 한국, 10-2014-0049498 (2013)
심재윤,최승남,서윤재, 공통 게이트 스위치를 이용한 클래스 AB 증폭장치 및 방법, 한국, 10-2013-0144191 (2013)
심재윤,류현석,김준석, STDP 동작을 위한 하나의 트랜지스터와 하나의 멤리스터를 가지는 시냅스 회로, 한국, 10-2013-0061924 (2013)
심재윤,류현석,김준석, 뉴로모픽 칩의 스파이크 이벤트 정보 전송 방법 및 장치, 및 뉴로모픽 칩, 한국, 10-2013-0050544 (2013)
심재윤,조화숙, 아날로그 디지털 변환기의 커패시터 부정합 효과를 줄이기 위한 커패시터 분할 및 교환을 통한 디지털 배경 보정기법, 한국, 10-2013-0018365 (2012)
심재윤,이준행,류현석, STDP 기능 셀을 위한 시냅스, STDP 기능 셀 및 STDP 기능 셀을 이용한 뉴로모픽 회로, USA, 13/490,699 (2012)
심재윤,허영도,하현수, 기준 전압 생성기, 한국, 10-2009-0070118 (2012)
심재윤,류현석,이준행, STDP 기능 셀을 위한 시냅스, STDP 기능 셀 및 STDP 기능 셀을 이용한 뉴로모픽 회로, -, PCT/KR2012/0031 (2012)
심재윤,류현석,이준행, STDP 기능 셀을 위한 시냅스, STDP 기능 셀 및 STDP 기능 셀을 이용한 뉴로모픽 회로, 한국, 10-2011-0054972 (2012)
심재윤,지동우, 델타-시그마 변조방식을 이용한 노이즈 세이핑 시간-디지털 변환기, USA, 13/329,983 (2011)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 헝가리, 09160865.3 (2011)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, Italy, 09160865.3 (2011)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 프랑스, 09160865.3 (2011)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 영국, 09160865.3 (2011)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 독일, 09160865.3 (2011)
심재윤,이준행,류현석,박근주,신창우, 뉴로모픽 칩에서 불일치를 자가 보정하는 장치 및 방법, 한국, 10-2011-0074387 (2011)
심재윤,이준행,류현석,박근주,신창우, 뉴로모픽 칩에서 스파이크 이벤트를 송수신하는 송수신장치 및 방법, 한국, 10-2011-0074388 (2011)
심재윤,지동우, 델타-시그마 변조방식을 이용한 노이즈 세이핑 시간-디지털 변환기, 한국, 10-2011-0113003 (2011)
심재윤,이중호,박승진,우수호, 반도체 장치의 온도정보 출력회로 및 온도정보 출력방법, 한국, 10-2009-0044129 (2011)
심재윤,장동비,김호영,김영상, 딜레이 매트릭스를 구비하는 광대역 다중 위상 출력 지연동기 루프 회로, USA, 12/028,936 (2010)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, USA, 12/673747 (2010)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, USA, 12/673,747 (2010)
심재윤,이선규, 시간 증폭기를 이용한 하위-지수 방식의 시간-디지털 변환기, USA, 12/795,221 (2010)
이선규,심재윤, 시간 증폭기를 이용한 하위-지수 방식의 시간-디지털 변환기, USA, 121795221 (2010)
심재윤,이선규, 위상차 증대기를 이용한 하위-지수 방식의 시간-디지털 변환기, 한국, 10-2010-0044818 (2010)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, USA, 12/663,732 (2010)
심재윤,김영상,김호영,장동비, 딜레이 매트릭스를 구비하는 광대역 다중 위상 출력 지연동기 루프 회로, 중국, 200810142879.8 (2009)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, PCT, PCT/KR2009/0057 (2009)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, -, PCT/KR2009/0057 (2009)
심재윤,이선규, 저전압/저전력 아날로그 디지털 변환기에 적합한 시간영역 전압 비교기, 한국, 10-2009-0090204 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 중국, 200910146412.5 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 일본, 2009-154820 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, USA, 12/472,425 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, -, 09160865.3 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, EP, 09160865.3 (2009)
이재구,우경철,최준,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, 중국, 200910146411.0 (2009)
이재구,우경철,최준,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, 일본, 2009-154819 (2009)
이재구,우경철,최준,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, USA, 12/455,227 (2009)
우경철,최준,이재구,심재윤,김경태, 저온 플라즈마를 이용한 지혈장치, USA, 12/455,227 (2009)
이재구,우경철,최준,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, -, 09160585.7 (2009)
이재구,우경철,최준,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, EP, 09160585.7 (2009)
이재구,최준,심재윤, 마이크로파 플라즈마 생성을 위한 휴대용 전력 공급 장치, 한국, 10-2009-0013574 (2009)
최준,우경철,심재윤,김경태,이재구, 저온 플라즈마를 이용한 지혈 및 상처 소독, 한국, 10-2008-0117285 (2008)
이재구,최준,우경철,심재윤,김경태, 저온 플라즈마를 이용한 지혈 및 상처 소독, 한국, 10-2008-0117285 (2008)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, PCT, PCT/KR2008/0012 (2007)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, -, PCT/KR2008/0012 (2007)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, 한국, 10-2007-0085300 (2007)
심재윤,김영상,김호영,장동비, 딜레이 매트릭스를 구비하는 광대역 다중 위상 출력 지연동기 루프 회로, 한국, 10-2007-0014563 (2007)
심재윤, 병렬 데이터 전송을 위한 분할된 집합 반전 인코딩 방법, 한국, 10-2005-0108840 (1992)